Implications of Register and Memory Temporal Locality for Distributed Microarchitectures

We explore various intervals between register assignments and the subsequent uses of the same registers. We also explore memory stores and the subsequent loads to the same memory addresses. Three di erent types of access intervals are de ned and data are gathered on them using benchmarks. This data serves to provide insight about how a distributed microarchitecture might take advantage of the register or memory access behavior in order to reduce the overhead of accessing centralized machine resources like a register le (in the case of register operations) or the memory hierarchy in the case of memory operations. A proposed distributed microarchitecture is brie y presented and data about its ability to allow operand bypassing of centralized machine resources to satisfy memory load requests is provided.